Analog Hardware Tolerance of Soft Competitive Learning

This paper examines issues in the analog CMOS circuit implementation of the soft competitive neural learning algorithm. Results of simulations based on actual measurements of previously fabricated analog components, primarily CMOS Gilbert multipliers, are presented. These results demonstrate that a generalized version of the soft competitive learning algorithm is capable of discovering appropriate features in an unsupervised learning mode. At the same time it is also well suited to fabrication in an analog environment, and inherent fabrication variations, such as transistor threshold variation and circuit noise, do not adversely effect the performance of the algorithm on a selected test problem.